The present invention relates to metal-based semiconductor circuit substrates and a process for producing the same. Particularly, the present invention relates to metal-based semiconductor circuit substrates which are light and easy to process and whose bonding reliability to an external circuit substrate is excellent, and a process for producing the same.
These days metal-based semiconductor circuit substrates have been used extensively in industry to produce semiconductor packages of microcomputers, microprocessors and other devices.
Typical examples of metal-based semiconductor circuit packages include a metal-based ball grid array (BGA) package disclosed in U.S. Pat. No. 5,420,460 and a metal-based metal quad package (MQP) disclosed in JP-A-6-53621 (Tokkaihei) (U.S. Pat. No. 5,639,990). The latter discloses that a metal-based wiring substrate is drawn to be box-shaped and that leads are formed in the periphery of its opening to obtain an MQP.
It is said that metal-based semiconductor substrates have characteristics such as heat radiation and electromagnetic shielding properties. A metallic body, which is used for a metal-based semiconductor circuit substrate, plays a part in reinforcing its circuit, in releasing heat generated in a semiconductor or in passing electricity to the ground. In a metallic body, a circuit is formed on its top surface and its bottom surface is opposite to the top surface. The bottom surface plays a part in releasing heat generated in a metal-based semiconductor circuit substrate and in absorbing infrared rays (IR) in mounting the metal-based semiconductor circuit substrate to a mother board by IR reflowing. In some cases the bottom surface plays a part in insulating.
JP-A-07-321250 (Tokkaihei) (U.S. Pat. No. 5,583,378) discloses that a protective layer, made of epoxy resin or suitable material other than epoxy resin, can be formed on the bottom surface of a conventional metal-based semiconductor circuit. The bottom surface plays a part just in protecting the conventional metal-based semiconductor circuit substrate. The bottom surface is usually the surface of a stainless steel plate or copper plate treated with zinc chromate, or is covered with a protecting layer of nickel (Ni) plating, a protecting layer consisting of nickel and gold (Au) plating layers or an epoxy resin layer.
When the bottom surface of a metallic body is not covered with an epoxy resin layer, the bottom surface has a small coefficient of radiation heat transfer, a small amount of radiation in heat release and a small amount of IR absorbed in a reflowing furnace, especially, an IR reflowing furnace. The temperature of a package is lower than that of a QFP or other parts mounted on a mother board in a reflowing furnace. Therefore, there is a narrow margin for the conditions of a reflowing furnace in which various parts are mounted at the same time; thus, the solder bonding becomes unstable.
Especially when a metal-based circuit substrate is produced to form a circuit, wire bond pads are nickel- and gold-plated at the same time as its bottom surface. The bottom surface is gold-plated although gold plating is unnecessary; therefore, gold plating increases the production costs of the metal-based semiconductor circuit substrate. Copper (Cu) is often used for a metallic body because of thermal and electric properties. In these cases, a type of a bimetal is formed because a nickel plating layer has a smaller coefficient of thermal expansion than a copper body; thus, changes in temperature bring about the deformation of a package.
A metal-based semiconductor circuit substrate having a metallic body of 0.1 to 0.4 mm in thickness is defined as a thin metal-based semiconductor circuit substrate. A stainless steel or copper plate is often used for a metallic body of a thin metal-based semiconductor circuit substrate. Especially a plate of copper or copper alloy, which has excellent heat transfer and electric properties, is often used. However the resulting circuit substrate has less flexural rigidity and is easy to deform due to temperature changes.
A warp appears when materials with different coefficients of thermal expansion are used for a metal-based semiconductor circuit substrate. Typical examples of coefficients of thermal expansion at 25.degree. C. are almost as follows:
(1) a layer consisting of Ni- and Au-plating layers: 13.times.10.sup.-6 /deg. PA1 (2) a metallic body made of stainless steel, copper or a copper alloy: 17.times.10.sup.-6 /deg. PA1 (3) a polyimide resin layer for insulating a circuit: 20-55.times.10.sup.-6 /deg. PA1 (4) a copper foil for a circuit: 17.times.10.sup.-6 /deg. PA1 (5) a layer of resist ink: 60-80.times.10.sup.-6 /deg. PA1 (a) a polyimide laminate which has a two-layer structure and consists of a layer of thermoplastic polyimide resin (1) and a layer of non-thermoplastic polyimide resin: PA1 (b) a polyimide layer which has an one-layer structure and consist s of a layer of thermoplastic polyimide resin (2) or the above-mentioned layer of non-thermoplastic polyimide resin as shown in (a): PA1 (c) a polyimide laminate which has a three-layer structure and consists of a layer of thermoplastic polyimide resin (1) as shown in (a), a layer of non-thermoplastic polyimide resin as shown in (a) and a layer of thermoplastic polyimide resin (2) as shown in (b):
When a laminate is observed from the viewpoint of coefficients of thermal expansion as shown above, the coefficients of thermal expansion ascend in the z-axis direction. When the temperature of a circuit substrate is increased, a warp appears so that its bottom surface becomes concave.
When a metallic body is at most 0.4 mm thick, especially at most 0.2 mm thick, it has less flexural rigidity. An example is disclosed in a display of High Performance Cavity-Down Metal-Based BGA (MeBGA) Package (TECHNICAL DIGEST, page 153), published in the Third VLSI PACKAGING WORKSHOP of Japan, December, 1996. When a semiconductor substrate has holes for detecting terminals in its metallic body, the metallic body, on which balls are mounted, decreases in area and the semiconductor substrate further decreases in flexural rigidity. When the temperature of the semiconductor substrate is increased, a warp becomes large. When a semiconductor substrate is mounted on a mother board with solder balls, for example, the semiconductor substrate is excellent in flatness at 25.degree. C. and can be mounted easily. However, a warp appears in the substrate at a melting temperature of solder balls of 185.degree. C.; thus, the solder balls in the corners are raised and suitable solder ball bonding is prevented. A warp appears in a semiconductor substrate when the temperature of the semiconductor substrate changes. When the semiconductor substrate is mounted on a mother board, such a warp is a large influence on the bonding reliability of solder balls.
The equation of Coffin-Manson was used to simulate the bonding reliability of solder balls, based on a stress analysis method. It is shown that the life of solder ball bonding varies in the range of many times or over according to the size of a warp.
The following method are considered to solve these problems.
The first method is to form an epoxy resin layer with a large coefficient of thermal expansion on the bottom surface of a metallic body. The second is to increase a metallic body in thickness and flexural rigidity in order to counter a stress resulting from the difference between coefficients of thermal expansion. The third is to use as a metallic body a metal with an extraordinarily large amount of flexural rigidity in order to increase the metallic body in flexural rigidity and to counter a stress resulting from the difference between coefficients of thermal expansion. The fourth is to use a polyimide resin having a smaller coefficient of thermal expansion in order to insulate a circuit. The fifth is to use a solder resist layer thinner than conventional solder resist layers. The sixth is to use a solder resist having a smaller coefficient of thermal expansion.
When an epoxy resin layer is formed on the bottom surface to improve IR absorption and counter a warp, the epoxy resin layer, however, accompanies various problems. The first problem appears when an epoxy resin layer is formed on the bottom surface of a metallic body in advance and the metallic body is used. When a cavity structure is formed by drawing, cracks appear in the epoxy resin layer and the resulting metal-based semiconductor circuit substrate deteriorates in durability and reliability as well as in appearance. The second appears when a resin layer is formed on a part of the bottom surface other than a drawing part using an epoxy-type resist ink in order to avoid cracks. When the resulting substrate is drawn, the substrate's drawing shape deteriorates in precision due to the difference in level between a place where a resin layer is formed and a place where no resin layer is formed. Such a substrate is unsuitable for mounting a semiconductor. The substrate also needs a mask so that the metallic body in the drawing part, exposed during forming a circuit on the top surface, is prevented from being exposed to an etching solution.
The third appears when detecting terminals are formed on the bottom surface due to a fine pattern. It is difficult to form an epoxy resin layer only on a part of the bottom surface where there are no detecting terminals. It is also possible that a cavity is formed and then an epoxy resin layer is formed by electrodeposition. This case, however, accompanies high production costs. Due to adhesive property, used in an epoxy resin which has a lower glass transition temperature and is softer. When such an epoxy resin is used in wire bonding, it is tacked to a jig for heating a substrate. In some electronic circuits, unnecessary parts are coated by electrodeposition using an epoxy resin.
When a thick metallic body is used, the resulting metal-based semiconductor circuit substrate becomes heavy and causes a circuit and a dielectric layer under the circuit to stretch to a considerable degree in drawing and bending. Therefore, when such a circuit substrate is drawn or bent, it is limited in curvature radius due to the stretch of the dielectric layer.
When a metallic body is increased in flexural elastic modulus, there is a limit in that the metallic body deteriorates in bending and drawing.
It is effective to use a polyimide resin having a lower coefficient of thermal expansion in order to insulate a circuit. However, even the polyimide resin cannot counter a solder resist layer having a large coefficient of thermal expansion. A polyimide resin having a lower coefficient of thermal expansion deteriorates in lamination and adhesive properties. The rate of etching with a liquid or a plasma gas is slow. The polyimide resin hinders the formation of via holes. The resulting substrate has a large amount of flexural rigidity and a small elongation percentage. When such a substrate is drawn, the size of its curvature radius is limited and the processing accuracy decreases.
When a solder resist layer is thinner than ordinary resist layers, the solder resist layer deteriorates in reliability.
It is preferred to use a solder resist having a coefficient of thermal expansion smaller than 30.times.10.sup.-6 /deg. It has been impossible to obtain a solder resist, which is photosensitive, can enable to form a fine pattern and has a coefficient of thermal expansion of at most 30.times.10.sup.-6 /deg.
It has been difficult to improve a thin metal-based semiconductor circuit substrate in IR absorption in a reflowing furnace and give plating resistance during keeping its drawing property. Especially, due to various reasons, it has been difficult to reduce the variations in shape of a thin metal-based semiconductor circuit substrate when the temperature of the substrate changes.
FIG. 1 illustrates one of conventional metal-based semiconductor circuit substrates. Metallic body 001 of at least 0.1 mm to at most 5 mm in thickness, dielectric layer 010 of at least 5 .mu.m to at most 200 .mu.m in thickness and electric conductor circuit layer 100 of at least 0.5 .mu.m to at most 100 .mu.m in thickness are laminated one over another in this order. Protective layer 300 such as nickel plating layer and other layers is on the bottom surface of the metallic body. In some cases, metallic body 001 and electric conductor circuit layer 100 are partly connected to each other with blind via hole (hereinafter referred to as BVH) 200.
FIG. 2 illustrates one of conventional metal-based semiconductor circuit substrates. Dielectric layers 010 and 011 and electric conductor circuit layers 100 and 101 are laminated on a metal-based semiconductor circuit substrate. The substrate has a multi-layered structure. Multi-layered electric conductor circuit layers 100 and 101 are optionally interlayer connected with BVH, interstitial via hole 201 (hereinafter referred to as IVH), through hole (hereinafter referred to as TH) and other connectors.
FIG. 3 also illustrates one of conventional metal-based semiconductor circuit substrates. A part of electric conductor circuit layer 100 is connected to metallic body 001 with BVH 200. A part of the metallic body just under the BVH is processed to form detecting terminal 400 being independent of the metallic body.
Preparation methods of these conventional semiconductor circuit substrates are exemplified as follows.
1) A dielectric sheet and an electric conductor foil are laminated on a metallic body with an adhesive or by use of the adhesive property of the dielectric sheet itself. A circuit is formed in the electric conductor foil according to well-known method. A resist layer is formed on the laminate according to a well-known method. The thus-obtained laminate is Ni-plated or Ni- and Au-plated according to a well-known method.
2) A laminate, formed with a dielectric sheet and an electric conductor foil, is used to form a circuit in the electric conductor foil according to a well-known method. A resist layer is formed on the laminate according to a well-known method. The thus-obtained laminate is Ni- and Au-plated to form a sheet with a circuit according to a well-known method. The laminate is adhered to a metallic body with an adhesive or by use of the adhesive property of the dielectric sheet itself.
3) A dielectric sheet is laminated on a metallic body. An electric conductor circuit is formed on the laminate according to the so-called additive process. A resist layer is formed on the laminate according to a well-known method. The thus-obtained laminate is Ni- and Au-plated according to a well-known method.
4) Epoxy resin is electrodeposited on the bottom surface of the metal-based semiconductor circuit substrate formed according to the above-mentioned Exemplified Methods 1) to 3); thus, an insulating material layer is formed on the bottom surface to give an insulated bottom surface.
5) Bottom surfaces of metallic bodies used in the above-mentioned Exemplified Method 1) to 3) are coated with an epoxy resin in advance.
In the above-mentioned Exemplified Method 1) to 3), the bottom surface of a metal-based semiconductor is also plated as well as wire bond pads (WB pads) on the top surface of it are Ni- and Au-plated. In the above-mentioned Exemplified Method 2), a rustproof layer such as nickel plating layer and other protective layers is often formed on a metallic body and then a sheet with a circuit is laminated on the metallic body. In the above-mentioned Exemplified Method 4), an epoxy resin layer is formed on the bottom surface. The bottom surface is often covered with a protective layer consisting of a metal or an epoxy resin having a property of rust proofing in any case. Therefore, the above-mentioned various problems happen.